Multi-channel ac conflict monitor

ABSTRACT

A circuit is provided for monitoring the signals displayed by a traffic signal system to detect the displaying of conflicting signals to two or more traffic paths. The circuit includes sensors responsive to the energization of the traffic signal lights and logic elements for determining when conflicting signals are displayed. The signal controller can override the monitor circuit to permit certain normally conflicting signal combinations. Additional logic elements in the circuit determine whether overlaps are permissible with the normal signal displays. When the circuit detects a conflict or an improper overlap, it transfers signal light operation from the normal sequencing mode to a flashing mode.

United States Patent Aug. 26, 1975 Hill [54] MU LTl-CHANNEL AC CONFLICTMONITOR [75] Inventor: Frank W. Hill, Moline, Ill.

[73] Assignee: Gulf & Western Industries, lnc.,

New York, NY.

[22] Filed: Oct. 7, 1974 [21] Appl. No.: 512,874

[52] US. Cl. 340/41 R; 340/248 A [51] Int; Cl. GOSG l/08 [58] Field ofSearch 340/41 R, 37

[56] References Cited UNITED STATES PATENTS 3,828,307 8/1974 Hungerford340/41 R Primary Examiner-Thomas B. Habecker Attorney, Agent, orFirmColton & Stone, lnc.

57 ABSTRACT A circuit is provided for monitoring the signals displayedby a traffic signal system to detect the displaying of conflictingsignals to two or more traffic paths. The circuit includes sensorsresponsive to the energization of the traffic signal lights and logicelements for determining when conflicting signals are displayed. Thesignal controller can override the monitor circuit to permit certainnormally conflicting signal combinations. Additional logic elements inthe circuit determine whether overlaps are permissible with the normalsignal displays. When the circuit detects a conflict or an improperoverlap, it transfers signal light operation from the normal sequencingmode to a flashing mode.

15 Claims, 11 Drawing Figures I6 '2 26 20 LOCAL i: LOAD 3 CONTROLLERSWITCHES i 34 34 FLASHER d 30 a CONTROL CONFLICT 22 MONITOR PAIENTEU M261975 SHEET 1 OF LOCAL CONTROLLER 00 m 37 m w 2w. m 2 6 G l5 Em H2 6 Mm nnR H8 H3 M EDI 6688224 0 1 B 111 AT 5577II s PT MU P cm W% 887 M111517.. /1 RW SP 775 6 T m 444 S $1 mm 332244 CD: ,1 1, 1, W 2 33 I E M4567 H P F IG. 2

2 SIGNAL LOAD SWITCHES CONFLICT MONITOR I4 LOCAL CONTROLLER FIG. 4

PII'IIEI-ITTIII INPUT I III INPUT2 INPUTI U2 INPUT 2 INPUT3 INPUT I (2)5INPUT 2 INPUT 3 INPUTI (2J6 INPUT 2 INPUT 3 INPUTI Us INPUT 2 INPUT 3INPUTI N4 INPUT2 INPUT3 INPUT I INPUT 2 INPUT 3 i-- CONVERTER AC TO DCSENSOR AND SHEET 2 [IF 5 -SEE FIG. 58

BI 62 65 66 63 64 7 I I I I AC TO DC SENSOR AND CONVERTER AC TO DCSENSOR AND CONVERTER AC TO DC SENSOR AND CONVERTER AC TO DC AMA VAIAMIASENSOR AND CONVERTER AC TO DC SENSOR AND CONVERTER AC TO DC SENSOR ANDCONVERTER AC TO DC SENSOR AND INPUT 3 l CONVERTER INPUT l UT INPUT2INPUT3 SEE FIG. 5D

BARRIER CHECK INHIBIT SEE FIG. 5B

PATENTEU AUI326I975 SEE FIG. 5A

FIG, 5B

SHEET 3 BF g3 AC TO DC SENSOR 8i CONVERTER INPUT INPUT I OLI SENSOR &

AC TO no CONVERTER INPUT INPUT AC TO DC SENSOR &

INPUT INPUT l 2 AC TO DC SENSOR 81 CONVERTER I I INPUT INPUT CONVERTERI, 73

SEE FIG. 5C

MULTI-CHANNEL AC CONFLICT MONITOR BACKGROUND OF THE INVENTION Thepresent invention pertains to traffic light controllers and, moreparticularly, to systems for monitoring the operation of traffic lightcontrollers to prevent the displaying of conflicting traffic controllingsignals.

The control of vehicular and pedestrian traffic at intersections iscommonly accomplished by the use of traffic light systems providingcommand signals to the motorists and pedestrians to regulate the orderlyflow of traffic. These signal systems normally operate under the controlof a local controller which sequentially actuates the individual signallights to provide proceed (green or WALK), caution (yellow) or stop (redor DON T WALK) signals. Under normal operating conditions, thecontroller sequence is such that proceed or caution signals will begiven only to those traffic flow patterns which are not in conflict withone another. In the event of a malfunction of the system, however,permissive indications such as proceed or caution signals may be givento conflicting traffic flow routes. Such malfunctioning presents ahazardous situation as'motorists frequently tend to rely on the trafficsignal commands. Also, even when the motorists are aware of themalfunctioning, the smooth flow of traffic may be impeded as motoristsare often hestitant to proceed through the intersection in such asituation.

Experience has shown that when a traffic light controller malfunctions,the least disruption of traffic flow results if the sequencing of thesignal lights by the controller is interrupted and the lights caused toflash a caution indication. A number of arrangements have been designedto monitor signal operation and to effect transfer of the signal lightfrom a sequencing mode to a flashing mode in the event of a malfunction.Clark et al U.S. Pat. No. 3,629,802, assigned to the assignee of thepresent application, discloses an error detection system having a logicnetwork receiving inputs corresponding to each possible permissivesignal indication and operable to produce an error signal if two or moreconflicting permissive signal indications are displayed at the sametime. The error detection system of this patent does not provide,however, for variations in the traffic signal operating sequence. InJarko et al U.S. Pat. No. 3,778, 762, a traffic signal controlmonitoring device is disclosed which is operative to produce an errorsignal in the event conflicting permissive signal indications aredisplayed and which includes a programming capability permitting themonitoring circuit to be adapted to different signal control sequences.While the Jarko et al system provides a degree of flexibility over theClark et al system, the modification of the monitor is accomplished bythe use of a wiring matrix or the like and, thus, requires manualchanges to adapt the unit to different signal sequencing patterns. Inother words, while the Jarko et al monitor may be readily adapted foruse with a variety of sequencing patterns, it is not capable ofautomatically accommo dating variations in a sequencing pattern.

A primary object of the present invention is the provision of a systemfor monitoring the operation of a traffic control signal to detectmalfunctions of the signal and to transfer the signal operation from asequencing mode to a flashing mode in the event conflicting trafficcontrol signals are given.

Another object of the present invention is the provi sion of a trafficsignal conflict monitor which may be employed with a variety ofdifferent control sequences without the necessity of rewiring or othermodification of the conflict monitor.

A further object of the present invention is the provi sion of a trafficsignal conflict monitor which may be controlled to permit normallyconflicting signal indications to be displayed when special trafficmovement patterns are required.

Yet another object of the present invention is the provision of atraffic signal conflict monitor which employs solid state logiccircuitry furnishing a high level of reliability.

BRIEF DESCRIPTION OF THE INVENTION The above and other objects of thepresent invention which will become apparent in the following detaileddescription of the preferred embodiment are achieved by the provision ofa conflict monitor having an input circuit associated with each trafficmovement phase, receiving an AC signal from each line switch associatedwith the respective phase and producing a DC signal during the timeinterval in which any of the respective line switches are energized; afirst solid state logic network comprised of a plurality of AND gateseach of which receives the output signals of two of the input circuitsassociated with conflicting phases and producing an output signalwhenever the two phases are in conflict; a second solid state logicnetwork having a pair of OR gates receiving, respectively, the outputsig nals of first and second groups of input circuits with the groupsbeing arranged so that any one phase of either group is in conflict withany phase of the other group, and an AND gate responsive to the outputsof the OR gates to produce an output signal in the event a conflictoccurs between any phase of one group and any phase of the other group;means under the control of the signal controller for disabling thesecond logic network in the event a normally conflicting signalindication is to be intentionally displayed; a relay operable to switchthe signal operation from a sequencing mode to a flashing mode; a timingcircuit responsive to the output of each of the AND gates and operableto actuate the relay; an additional input circuit associated with eachoverlap function and producing a DC signal whenever the overlapindication is being displayed; and an over lap monitoring circuit foreach overlap function including a solid state logic network programmablefor determining which overlap signals are permissible with the phaseindications, each overlap monitoring circuit including an AND gateproducing an output signal in the event the phase and overlap displaysare conflicting, the output signal of each of these AND gates alsoproviding an actuating input to the timing circuit. The conflict monitormay also include means for monitoring the signal controller operatingvoltage and operable to transfer signal operation from a sequencing modeto a flashing mode in the event the operating voltage deviates from itsnormal level.

For a more complete understanding of the invention and the objects andadvantages thereof, reference should be had to the following detaileddescription and the accompanying drawings wherein there is shown apreferred embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings:

FIG. 1 is a diagrammatic plan view of a typical street intersection withtraffic movements or phases indicated by arrows;

FIG. 2 is a chart giving the conflicting and compatible phases oftraffic movement through the intersection of FIG. 1;

FIG. 3 is a chart illustrating a relationship between the phases oftraffic movement through the intersection of FIG. 1;

FIG. 4 is a block diagram of a traffic signal control systemincorporating the conflict monitor of the present invention;

FIG. Sa-e is a schematic showing of the conflict monitor of the presentinvention;

FIG. 6 is a schematic showing of the normal function input circuit ofthe conflict monitor;

FIG. 7 is a schematic showing of the overlap function input circuit ofthe conflict monitor; and

FIG. 8 is a block diagram showing the manner in which the sections ofFIG. are arranged.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT a typical intersection10 is shown in FIG. 1. The in tersection, formed by the crossing of anorth-south street and an east-west street, is provided with a trafficsignal 12 operated by a controller 14. The traffic signal 12 has aplurality of lights for providing traffic control signals to motorists.In the illustrated arrangement, the signal 12 provides proceed (green),caution (yellow) and stop (red) indications for each of the four throughmovements, designated I51, I53, I15 and 117, as well as each left turnmovement, designated )D ZJMJZK QIS. Pedestrian signals may also beincluded. It should be understood that the intersection and trafficmovement patterns of FIG. 1 were chosen for purposes of illustration andthat the control and conflict monitor of the present invention is notlimited to this arrangement.

As will be seen from FIG. 1, certain traffic move ments through theintersection 10 are compatible with one another while other movementsrepresent conflicting patterns. Thus, northbound traffic, phase onemovement (9 1), and southbound traffic, phase five movement (IIS) mayproceed simultaneously. Likewise, northbound traffic, phase one movement(I51), and north-to westbound turning traffic, phase six movement (I16),are compatible. However, northbound and westbound traffic flow, phaseone and phase three movements ((51 and 163), respectively, representconflicting movements which cannot occur at the same time. The chart ofFIG. 2 details the conflicting and compatible traffic movements for theintersection 10. This relationship of the compatible and conflicting phases of traffic movement is also illustrated in the chart of FIG. 3 whereany phase on one side of the barrier is in conflict with each of thephases on the opposite side thereof while any phase of either ring iscompatible with each of the phases in the other ring and on the sameside of the barrier.

Under certain circumstances, it may be desirable to display normallyconflicting signals to two or more phases of traffic movement. Forexample, where an intersection includes a railroad grade crossing, itmay be desirable to display green indications to the phase one,

phase three, phase five and phase seven movements following actuation ofthe crossing signals and prior to the passing of the train through theintersection to permit any vehicles within the intersection to moveclear thereof. As will be apparent in the description below, theconflict monitor of the present invention has the capability ofpermitting such a signal display without sensing such a display as anerror or malfunction.

Referring now to FIG. 4, the overall control and monitoring system foroperating the traffic signal 12 is illustrated. The controller 14includes switching means, either mechanical or solid state, which aresequentially operated to provide actuating signals over conductors 18 toload switches 16 which serve to connect the lights of signal 12 to an ACpower source by way of conductors 20. The conflict monitor 22 receivesan AC input signal from each of the load switches 16 over the conductors24. As will be described in greater detail below, the conflict monitor22 includes a logic network which determines whether the energizedsignal lights represent a compatible or a conflicting combination ofphases. A compatible combination of phases results in no output beingproduced by the conflict monitor 22. A conflicting combination ofphases, however, causes the conflict monitor 22 to override the localcontroller 14 by way ofline 28 and to actuate a flasher control circuit30 over line 32, placing the signal 12 in flashing operation.

The switching means of the controller 14 also provides command signalsfor overlap functions, signals being furnished over conductors 26 toenergize the load switches 16.

The conflict monitor 22 may also include means for monitoring theoperating voltage levels of the local controller 14 over the line 36 andwill transfer signal operation for the normal sequencing mode to theflashing mode of operation in the event the controller operatingvoltages depart from specified values.

The conflict monitor 14, illustrated schematically in FIG. 5, iscomprised of a normal function sensing and.

monitoring section (FIG. 5A), an overlap function sensing and monitoringsection (FIGS. 58 and 5C) and a relay control and switching section(FIG. 5D). A power supply circuit 40 is connected to an AC power sourceover the lines L1 and L2 and provides a regulated DC voltage for thelogic circuitry of the conflict monitor.

The normal function sensing and monitoring section includes an AC to DCsensor and converter 41-48 for each of the eight traffic movementphases. Each of the sensors has a plurality of input lines which areconnected to the line switches associated with the respec tive phases toreceive AC signals when the respective line switches are energized. Eachsensor 41-48 produces a DC output signal whenever an AC signal ispresent at any one of the inputs to the sensor. The sensor 41 associatedwith 01 is illustrated in greater detail in FIG. 6. Input signalspresent at the terminals a, b and c are connected across resistors R1,R2 and R3, respec tively, to diode pairs D10, D11; D12, D13; and D14,D15. The diodes of each pair are of opposite polarity to one another.The signals through the first diode of each pair D10, D12, D14 aresupplied across resistor R4 to the negative input of AC-DC converter U6while the signals across the second diode of each pair D11, D13, D15 aresupplied across resistor R5 to the positive input of the converter U6.The circuit is arranged so that a DC output signal is present at theterminal d whenever a full wave AC signal or a half-wave AC signal ofeither polarity is present at any of the input terminals a, b and The DCoutput signals of the AC to DC sensor and converter circuits 41-48 aresupplied to conductors 61-68, respectively. These conductors areconnected in pair-wise fashion to AND gates U3a, U3b, U3c and U3d. TheAND gate U3a receives the outputs of the sensor and converter circuits41 and 42 across resistors R79 and R77, respectively. The I55 and 1116signals are connected across the resistors R81 and R83, respec tively,to the AND gate U3b; the to and 4 signals,

across resistors R63 and R65, respectively to AND gate U3c; and the 07and 08 signals across resistors R69 and R67, respectively, to the ANDgate U3d. Each of the AND gates U3a-U3d is also connected to theregulated DC output of the power supply 40 over the resistors R41-R44,respectively.

In the illustrated embodiment of the conflict monitor circuit, the logicelements, including the AND gates U3a-U3d, are comprised of current typeoperational amplifiers. It should be understood, however, that theinvention is not limited to the use of logic elements of this type. Inthe following description of the monitor circuit and its operation,reference is made to logic ZERO and logic ONE signals. These terms areused in their conventional senses in logic circuit terminology and, inthe case of circuits employing current type operational amplifiers,denote the absence or presence of current signals.

As will be noted from the charts of FIGS. 2 and 3, the pair of inputs toeach of the AND gates U3a-U3d represent a pair of conflicting phases onthe same side of the barrier. Each of the AND gates U3aU3d operates toproduce an output, logic ONE, signal in the event input signals aresupplied by both of the sensor and converter circuits connected thereto.Thus, for example, if the line switches for both the 01 and 02 signal indications are energized, the DC currents from the sensor and convertercircuits 41 and 42 will be supplied across resistors R79 and R77,respectively, triggering the AND gate U3a to produce a DC output signalfrom this gate. As a result, a DC current is impressed across resistorR87 on the conductor 60. The AND gates U3b, U3c and U3d are alsoconnected to conductor 60 across the resistors R88, R86 and R85,respectively, so that the occurrence of 165 and Q16 signals together, 03and 04 signals together, or 07 and 08 signals together will result in alogic ONE signal in the conductor 60.

The conductor 60 provides the control input to an OR gate Ua. The ORGATE U5a is also connected to the power supply 40 over the resistor R60.The OR gate USa produces an output signal whenever a logic ONE signal ispresent on the conductor 60 and this output signal is supplied acrossdiode D21, resistor R90, operational amplifier USb, resistors 93 and 94to timer U50. If the input signal on conductor 60 to OR gate U5a remainspresent for the time interval determined by the timer U50, the timer U50then switches on the transistor Q6. Typically, the time interval imposedby timer U50 is 300MSil00MS. The switching. on of transistor Q6energizes release coil CR1-RC. When coil CR1-RC. When coil CR1-RC isenergized contact CR1 opens removing operating current from relay CR2-C.Deener gization of relay CR2-C causes the contacts CR2-1 and CR2-2 ofthis relaty to switch from their normal to reverse positions thusswitching conductor P9-F from the conductor P9-D to the conductor P9-Eand switching conductor P9-J from conductor P9-G to conductor P9-H.These conductors are connected to the controller and flash controlcircuits and, when switched to their reverse positions, cause control ofthe traffic signal 12 to switch from the normal or sequencing mode to aflashing mode of operation.

Opening of relay contact CR1-1 also causes the po tential across neonlamp PL2 to increase to the level at which this lamp conducts providinga visual indication that a conflict has occurred.

Relay CR1 is returned to its normal state by the closing of push buttonPBl which energizes the latching coil CR1-LC.

The output signals of the sensor and converter circuits 41, 42, 45 and46 are also connected across resis tors R80, R78, R82 and R84,respectively, to an input of OR gate U4a. As will be seen from FIG. 3,these four signals represent the four phases on the left side of thebarrier. The OR gate U4a is also connected to the power supply 40 acrossthe resistor R48 and this gate is operable to produce a logic ONE outputsignal upon the occurrence of a logic ONE signal from any one of thefour sensor and converter circuits connected thereto. The four sensorand converter circuits corresponding to the 03, 164, 07 and 08 sensorand converter circuits are also connected to an OR gate U4b. Thesesignals represent the four phases on the right side of the barrier ofFIG. 3. Diodes D18 and D20 connect the outputs of the OR gates U4a andU4b, respectively, to a conductor 69 which is also connected acrossresistor R45 to power supply 40 and across diodes D17 and resistor R46to the power supply 40. The conductor 69 is further connected through adiode D19 to one input of AND gate U40, the other input of which isconnected to the power supply 40 across resistor R47. AND gate U40operates to produce a logic ONE signal in the event logic ONE outputsignals are supplied from both OR gates U4a and U4b. The output signalof AND gate U40 is supplied across resistor R89 to the conductor 60.Thus, AND gate U40 will produce a logic ONE output signal whenever anyone phase on one side of the barrier and any one phase on the oppositeside of the barrier are attempted to be displayed at the same time.Since each phase on either side of the barrier is normally in conflictwith each phase on the opposite side of the barrier, this portion of thecircuit provides for the monitoring of cross-barrier conflicts. Theoperation of this portion of the circuit may be overridden by thecontroller 14 when it is desired to display crossbarrier conflictingsignals. This is accomplished through the terminal P9-R which provides aconnection to the controller 14. When a cross-barrier conflicting signaldisplay is desired, the terminal P9-R is grounded thus grounding theresistor R46 and, through the diode D17, the conductor 69 so that theoutputs of the OR gates U4a and U4b are grounded and AND gate U40 is notenergized.

An AC to DC sensor and converter circuit is provided for each of thefour overlap functions. Each of these circuits 5154 is of the type shownin FIG. 7 and, as will be seen from a comparison of FIGS. 6 and 7, differs from the AC to DC sensor and converter circuits associated with thenormal functions only in that the overlap function AC to DC sensor andconverter circuits 51-54 are provided with only two input terminals.

The circuit operates in the same manner as does the circuit of HO. 6,providing a DC current at the termi nal g whenever full or half wave ACsignals are present at either of the input terminals e or f. The DCoutput signals of the circuits 51-54 are supplied to conductors 71-74,respectively.

An overlap input control circuit is provided for each of the fouroverlap functions. The circuit 81 associated with overlap one (OL1) isshown in detail in FIG. B while the circuits 82-84 associated withoverlaps twofour (OL2-OL4), respectively, are shown in block diagrams inFIG. 5C, each of these latter three circuits being identical to thecircuit 81. The overlap input control circuit 81 includes NAND gatesUlla-d, Uad, each of which is connected to the regulated DC output ofpower supply 40 across resistors R97, R98, R100, R99, R101, R102, R104,R103, respectively. The control input terminal of NAND gate Ulla isconnected to the conductor 61 across resistor R3 and to the power supply40 across resistors R1 and R2. The junction of resistors R1 and R2 isalso connected to a terminal 01- OL1. Similar connections are providedfor the second terminal of each of the remaining NAND gates of thecircuit 81. The output of each NAND gate is connected through a diodeD1D8, respectively, to a bus 79 which is also connected across resistorR137 to the regulated DC output of power supply circuit 40. The bus 79is also connected across diode D33 to the input of an additional NANDgate U2a. NAND gate U2a is connected to the regulated DC output of powersupply circuit 40 across resistor R161. The output of NAND gate U2aprovides one control input, across resistor R165, to AND gate Ula. Asecond control input to AND gate Ula is derived from the overlap one ACto DC sensor and converter circuit 51 over conductor 71 and resistorR166. The AND gate Ula is connected to the regulated DC power supplyacross resistor R147. The overlap input control circuits associated withoverlaps two, three and four provide control inputs to NAND gates U2b, Uand U2d, respectively, and the output of each of these NAND gates isdirected to an AND gate Ulb, Ulc', Uld, respectively, with each of theseAND gates receiving a second control input from the corresponding AC toDC sensor and converter circuits 52, 53, 54, respectively. The outputsof the AND gates U1aU1d are connected respectively to conductors 75-78which, in turn, are connected through resistors R173-Rl76 to theconductor 60 which provides the control input to the timer circuit ORgate USa.

A switching transistor Q1 has its base connected to the output of theoverlap one AC to DC sensor and converter circuit 51 through resistorR177 and conductor 71. The emitter of transistor O1 is grounded whilethe collector is connected to terminal OLl Control. Transistor O1 isnon-conducting except when a signal is supplied from the sensor andconverter circuit 51. Each of the control inputs fi l-0L1 fl8-OL1 of theoverlap one input control circuit 81 which corresponds to a permissiblephase during the overlap one interval is connected to the OL] Controlterminal. For example, if phases one and five are a permissiblecombination during the overlap one interval, connections will beprovided between terminals ill-0L1 and XlS-OLI to the OLl Controlterminal. in order to provide flexibility in programming permissiveoverlap combinations, the inputs l-OL1 QiS-OLI and OLl Control areconnected to a terminal strip and jumper wires are employed to effectthe desired interconnections. Transistors Q2, Q3 and Q4 are similarlycontrolled by the sensor and converter circuits 52, 53 and 54,respectively, and provide input control signals to the overlap inputcontrol circuits 82, 83 and 84, respectively.

During the overlap one interval, the controller 14 energizes the ones ofthe load switches 16 which correspond to the signal lights of theindications being displayed. The sensor and converter circuit 51 detectsthe signals from these load switches and produces an output signal onconductor 71. Transistor O1 is turned on and completes a connection toground for each of the control inputs of the overlap one input andcontrol circuit 81 which is connected to the OLl Control terminal If, asassumed above, phases one and five are permitted during the overlap oneinterval, the input terminals 01- OLl and TlS-OLI will be grounded whilethe remaining terminals ylZ-OLI l4-oLl and fi 6-OL1 fs-0L1 will not begrounded. A logic ONE input is thus provided to NAND gate Ullb acrossresistors R4 and R5 and, in a similar manner the NAND gates Ullc, Ulld,U10- bU10d will all receive logic ONE inputs across the correspondingresistors. Assuming that the phase one and five displays are the onlydisplays occurring during the overlap one interval, the phase one AC toDC sensor and converter 41 will, during the phase one interval, supply asignal to conductor 61 which is sensed by the NAND gate Ulla acrossresistor R3 as a logic ONE input while the phase five AC to DC sensorand converter 45 will supply a signal to conductor 65 which is sensed bythe NAND gate U10a across resistor R15 as a logic ONE input. Since thefill-0L1 and 5-OL1 contacts are grounded, the NAND gates Ulla and U10asee only one logic ONE input each and thus pro duce logic ONE outputs tothe bus 79. The remaining NAND gates of the circuit 81 are alsoreceiving only one logic ONE input each and thus also produce logic ONEoutputs to the bus 79. The NAND gate U2a thus sees all logic ONE inputsand, accordingly, produces a logic ZERO output which furnishes onecontrol input,

to the AND gate Ula. The occurrence of the overlap one display (OL1)during this time period causes the overlap one AC to DC sensor andconverter 51 to produce a signal in conductor 71 which supplies a logicONE input to the AND gate Ula. Since, however, the second input to thisAND gate is ZERO, the Ula AND gate produces a ZERO output signal,indicating that overlap one is permissible. If the controller attemptsto display a phase which is not permissible during the overlap oneinterval, at least one of the NAND gates Ulla-Ulla, U10aU10d willreceive two logic ONE inputs. For example, if the controller 14 advancesto the phase two interval, the phase two AC to DC sensor and convertercircuit 42 produces an output signal on the conductor 62 which is sensedby the NAND gate U1 11; across resistor R6 as a logic ONE input. Sincethe 152-0151 terminal is not grounded, the NAND gate Ullb thus sees twologic ONE inputs and produces a logic ZERO output. The NAND gate U2athus senses a combination of logic ONE and logic ZERO inputs and,accordingly, produces a logic ONE output. If the overlap one displaycontinues during this second time interval, the logic ONE signal fromthe overlap one AC to DC sensor and converter 51 is also supplied as aninput to the AND gate Ula and this gate produces a logic ONE outputwhich, through conductor 75, resistor R173 and conductor provides alogic ONE input to the OR gate Ua of the timer circuit controlling theCR1 relay. Accordingly, the occurrence of the overlap one display duringthe phase two display interval is sensed as a conflict.

The conflict monitor also monitors the operating voltage level of thecontroller 14, a relay coil CR3-C being connected, through inputterminals P9-P and P9-N, to the controller circuitry. As long as thevoltage across the terminals P9-P and P9-N remains at the proper levelfor operation of the controller circuitry, the relay coil CR3-C remainsenergized holding relay contacts CR3-l and CR3-2 in their normalpositions. The contact CR3-l is normally open, disconnecting pilot lampPLl from the AC power source and this lamp is, accordingly, not lit aslong as the controller operating voltage level is maintained. in theevent the voltage across the terminals P9-P and P9-N drops below thelevel required for proper operation of the controller circuitry, relaycoil CR3-C releases, causing contacts CR3-l and CR3-2 to move to theirreverse positions. Lamp PLl is thus connected to the AC power supply andterminal P9-M is disconnected from terminal P9-K and connected toterminal P9-L, causing the traffic signal to operate in a flashing mode.

From the above description of the conflict monitor and the operationthereof, it should be apparent that the present invention provides asystem for monitoring the operation of a traffic signal which provides adegree of flexibility of signal display combinations which is notpresent in the conflict monitor systems of the prior art. Thisflexibility is achieved by the provision, in the conflict monitor, ofthe barrier check inhibit circuitry permitting the controller tointentionally effect otherwise conflicting phase displays and of theoverlap input control circuits permitting variation of permissible phasecombinations during overlap intervals.

While a preferred embodiment of the invention has been illustrated anddescribed in detail, the invention is not limited thereto or thereby.Rather, reference should be had to the appended claims in determiningthe scope of the invention.

What is claimed is:

1. In a traffic control system for controlling traffic movement over aplurality of traffic flow paths at least certain of which conflict withone another and having a traffic signal providing right-of-way and stopindications to each traffic flow path and a controller actuating saidtraffic signal; a conflict monitor, comprising:

a plurality of detector circuits, each detector circuit being associatedwith a different one of said traffic flow paths and producing an outputsignal during the time interval in which said traffic signal displays aright-of-way indication to said traffic flow path;

a plurality of first logic elements, each first logic element beingconnected to two of said detector circuits to receive the output signalstherefrom, the detector circuits connected to any one of said firstlogic elements being associated with conflicting traffic flow paths,each first logic element producing an output signal whenever bothdetector circuits connected thereto produce output signals;

a logic network connected to all of said detector circuits to receivethe output signals therefrom, said network producing an output signalwhenever an output signal is received from at least one detector circuitof a first group of detector circuits and an output signal is receivedfrom at least one detector circuit of a second group of detectorcircuits, each detector circuit of the first group being associated witha traffic flow path which conflicts with each traffic flow path withwhich the detectors of the second group are associated; and

circuit means for interrupting normal operation of said traffic signal,said circuit means being responsive to the output signals of each ofsaid first logic elements and of said logic network.

2. The conflict monitor of claim 1 further including means actuated bysaid controller for disabling said logic network.

3. The conflict monitor of claim 1 wherein said logic network includesfirst and second OR gates receiving, respectively, the output signals ofthe detector circuits of said first and second groups as input signalsand an AND gate receiving the output signals of said OR gates as inputsignals, the output signal of said AND gate being the output signal ofsaid logic network.

4. The conflict monitor of claim 3 wherein said controller includesmeans for blocking said OR gate output signals from said AND gate.

5. The conflict monitor of claim 1 wherein said circuit means includesrelay means for effecting interruption of said traffic signal operationand a relay actuating circuit responsive to the output signals of saidfirst logic elements and of said logic network.

6. The conflict monitor of claim 5 wherein said relay actuating circuitincludes timing means for delaying relay actuation until said lastmentioned output signals have been present for a predetermined timeinterval.

7. The conflict monitor of claim 1 wherein said traffic signal providesoverlap displays and said conflict monitor further includes a pluralityof additional detector circuits, one additional detector circuit beingassociated with each overlap display, each of said additional detectorcircuits furnishing an output signal during the interval in which thecorresponding overlap display is actuated;

a plurality of programmable circuits, one programmable circuit beingassociated with each overlap display, each programmable circuitreceiving the output signal of the corresponding additional detectorcircuit and producing, in response thereto, control signals indicatingthe permissible combinations of right-of-way indications during thecorresponding overlap; and

a second logic network receiving said output signals of each of saidfirst mentioned detector circuits, said output signals of saidadditional detector circuits and said control signals, said second logicnetwork producing an output signal whenever output signals are receivedfrom said first mentioned and said additional detector circuits in theabsence of a control signal, said second logic network output signalbeing supplied to said circuit means as an input signal thereto.

8. in a traffic control system for controlling the movement of trafficalong a plurality of paths through an intersection with at least certainof said paths being in conflict with one another and having a signallight and a controller actuating the signal light to provide normal andoverlap signal indications; a conflict monitor, comprising:

a plurality of first detector circuits, one circuit being provided foreach normal indication and producing an output signal during the timeinterval in which said normal indication is displayed;

a first logic circuit receiving the output signals of said firstdetector circuits and producing an error signal whenever at least twofirst detector circuit output signals corresponding to conflictingtraffic move ment paths are present;

an output circuit actuated by said error signal and operable tointerrupt normal operation of said signal light;

a plurality of second detector circuits, one circuit being provided foreach overlap indication and producing an output signal during the timeinterval in which said overlap indication is displayed;

a plurality of programmable circuits, one programmable circuit beingassociated with each overlap signal indication and receiving the outputsignal of the corresponding one of said second detector circuits toproduce, in response thereto, control signals indicating the permissiblenormal signal indi cations during the respective overlap; and

a second logic circuit receiving the output signals of said firstdetector circuits, the output signals of said second detector circuitsand said control signals, said second logic circuit producing an errorsignal whenever at least one first detector output signal and at leastone second detector output signal are received in the absence a controlsignal corresponding to the associated normal and overlap indications,said error signal providing an actuating input to said output circuit.

9. The conflict monitor according to claim 8 wherein said first logiccircuit includes a plurality of AND gates, each AND gate receiving theoutput signals of two of said first detector circuits corresponding toconflicting normal indications, the output signal of any AND gatecomprising said error signal.

10. The conflict monitor according to claim 9 wherein said first logiccircuit further includes at least two OR gates, each OR gate receivingthe output sig nals from a group of said first detector circuits, saidgroups being mutually exclusive and each normal indication associatedwith a detector circuit of one group being in conflict with each normalindication associated with a detector circuit of the remaining groups,each OR gate producing an output signal whenever an output signal fromat least one detector circuit of the corresponding group is present, andan additional AND gate receiving the output signals of each of said ORgates, said additional AND gate producing an output signal whenever atleast two OR gate output signals are present, said AND gate outputsignal comprising said error signal.

11. The conflict monitor according to claim 10 wherein each of saidgates comprises a current type operational amplifier.

12. The conflict monitor according to claim 8 wherein said second logiccircuit comprises a plurality of logic networks, one logic network beingprovided for each overlap indication, each logic network receiving saidoutput signals of each of said first detector circuits and said controlsignals for the corresponding overlap function and operable to producean output signal whenever a first detector circuit output signal isreceived in the absence of the corresponding control signal, and an ANDgate for each overlap indication, each of said AND gates receiving theoutput signal of the corresponding second detector circuit and thecorresponding logic network, the output signal of each of said AND gatesconstituting said error signal.

13. The conflict monitor according to claim 12 wherein each logicnetwork comprises a plurality of first NAND gates, one NAND gate beingprovided for each normal indication and receiving the output signal ofthe corresponding first detector circuit as an input signal, each logicnetwork including circuit means normally providing a second input signalto each of said first NAND gates, said programmable circuits being suchthat said control signals remove the second input signals from thecorresponding NAND gates, each network further including an additonalNAND gate receiving the output signals of each of said first NAND gatesas input signals, the output signal of said additional NAND gate beingthe output signal of said logic network.

14. The conflict monitor according to claim 13 wherein each of saidgates comprises a current type operational amplifier.

15. A conflict monitor for a traffic control system of the type having atraffic light for displaying normal phase and overlap signals to controltraffic movement through an intersection, certain of said normal phasemovements being in conflict with one another, said system including acontroller operating said traffic light; the conflict monitorcomprising:

a plurality of first input circuits, one input circuit being providedfor each normal phase and producing an output signal whenever saidnormal phase signal is displayed;

a first solid state logic network comprised of a plurality of AND gateseach of which receives said output signals of two of said input circuitsassociated with conflicting phases and producing an output signalwhenever said two phases are in conflict;

a second solid state logic network having a pair of OR gates receiving,respectively, said output signals of first and second groups of saidinput circuits with, the groups being arranged so that any one phase ofeither group is in conflict with any phase of the other group, and anAND gate responsive to the outputs of said OR gates to produce an outputsig nal in the event a conflict occurs between any phase of one groupand any phase of the other group;

means under the control of said signal controller for disabling saidsecond logic network in the event a normally conflicting signalindication is to be intentionally displayed;

a relay operable to switch the signal operation from a sequencing modeto a flashing mode;

a timing circuit responsive to the output of each of said AND gates andoperable to actuate said relay;

an additional input circuit associated with each overlap function andproducing an output signal whenever said overlap indication is beingdisplayed;

a programmable circuit associated with each overlap function, eachprogrammable circuit receiving the output signal of the correspondingadditional input circuit and producing, in response thereto, controlsignals indicating compatible normal phases during the correspondingoverlap; and

an overlap monitoring circuit for each overlap function including asolid state logic network receiving the output signals of said firstinput circuits, the

permissible phase display occurs during said overlap, the output signalof each of these AND gates also providing an actuating input to saidtiming circuit.

1. In a traffic control system for controlling traffic movemenT over aplurality of traffic flow paths at least certain of which conflict withone another and having a traffic signal providing right-of-way and stopindications to each traffic flow path and a controller actuating saidtraffic signal; a conflict monitor, comprising: a plurality of detectorcircuits, each detector circuit being associated with a different one ofsaid traffic flow paths and producing an output signal during the timeinterval in which said traffic signal displays a right-of-way indicationto said traffic flow path; a plurality of first logic elements, eachfirst logic element being connected to two of said detector circuits toreceive the output signals therefrom, the detector circuits connected toany one of said first logic elements being associated with conflictingtraffic flow paths, each first logic element producing an output signalwhenever both detector circuits connected thereto produce outputsignals; a logic network connected to all of said detector circuits toreceive the output signals therefrom, said network producing an outputsignal whenever an output signal is received from at least one detectorcircuit of a first group of detector circuits and an output signal isreceived from at least one detector circuit of a second group ofdetector circuits, each detector circuit of the first group beingassociated with a traffic flow path which conflicts with each trafficflow path with which the detectors of the second group are associated;and circuit means for interrupting normal operation of said trafficsignal, said circuit means being responsive to the output signals ofeach of said first logic elements and of said logic network.
 2. Theconflict monitor of claim 1 further including means actuated by saidcontroller for disabling said logic network.
 3. The conflict monitor ofclaim 1 wherein said logic network includes first and second OR gatesreceiving, respectively, the output signals of the detector circuits ofsaid first and second groups as input signals and an AND gate receivingthe output signals of said OR gates as input signals, the output signalof said AND gate being the output signal of said logic network.
 4. Theconflict monitor of claim 3 wherein said controller includes means forblocking said OR gate output signals from said AND gate.
 5. The conflictmonitor of claim 1 wherein said circuit means includes relay means foreffecting interruption of said traffic signal operation and a relayactuating circuit responsive to the output signals of said first logicelements and of said logic network.
 6. The conflict monitor of claim 5wherein said relay actuating circuit includes timing means for delayingrelay actuation until said last mentioned output signals have beenpresent for a predetermined time interval.
 7. The conflict monitor ofclaim 1 wherein said traffic signal provides overlap displays and saidconflict monitor further includes a plurality of additional detectorcircuits, one additional detector circuit being associated with eachoverlap display, each of said additional detector circuits furnishing anoutput signal during the interval in which the corresponding overlapdisplay is actuated; a plurality of programmable circuits, oneprogrammable circuit being associated with each overlap display, eachprogrammable circuit receiving the output signal of the correspondingadditional detector circuit and producing, in response thereto, controlsignals indicating the permissible combinations of right-of-wayindications during the corresponding overlap; and a second logic networkreceiving said output signals of each of said first mentioned detectorcircuits, said output signals of said additional detector circuits andsaid control signals, said second logic network producing an outputsignal whenever output signals are received from said first mentionedand said additional detector circuits in the absence of a controlsignal, said second logic network output signal being sUpplied to saidcircuit means as an input signal thereto.
 8. In a traffic control systemfor controlling the movement of traffic along a plurality of pathsthrough an intersection with at least certain of said paths being inconflict with one another and having a signal light and a controlleractuating the signal light to provide normal and overlap signalindications; a conflict monitor, comprising: a plurality of firstdetector circuits, one circuit being provided for each normal indicationand producing an output signal during the time interval in which saidnormal indication is displayed; a first logic circuit receiving theoutput signals of said first detector circuits and producing an errorsignal whenever at least two first detector circuit output signalscorresponding to conflicting traffic movement paths are present; anoutput circuit actuated by said error signal and operable to interruptnormal operation of said signal light; a plurality of second detectorcircuits, one circuit being provided for each overlap indication andproducing an output signal during the time interval in which saidoverlap indication is displayed; a plurality of programmable circuits,one programmable circuit being associated with each overlap signalindication and receiving the output signal of the corresponding one ofsaid second detector circuits to produce, in response thereto, controlsignals indicating the permissible normal signal indications during therespective overlap; and a second logic circuit receiving the outputsignals of said first detector circuits, the output signals of saidsecond detector circuits and said control signals, said second logiccircuit producing an error signal whenever at least one first detectoroutput signal and at least one second detector output signal arereceived in the absence a control signal corresponding to the associatednormal and overlap indications, said error signal providing an actuatinginput to said output circuit.
 9. The conflict monitor according to claim8 wherein said first logic circuit includes a plurality of AND gates,each AND gate receiving the output signals of two of said first detectorcircuits corresponding to conflicting normal indications, the outputsignal of any AND gate comprising said error signal.
 10. The conflictmonitor according to claim 9 wherein said first logic circuit furtherincludes at least two OR gates, each OR gate receiving the outputsignals from a group of said first detector circuits, said groups beingmutually exclusive and each normal indication associated with a detectorcircuit of one group being in conflict with each normal indicationassociated with a detector circuit of the remaining groups, each OR gateproducing an output signal whenever an output signal from at least onedetector circuit of the corresponding group is present, and anadditional AND gate receiving the output signals of each of said ORgates, said additional AND gate producing an output signal whenever atleast two OR gate output signals are present, said AND gate outputsignal comprising said error signal.
 11. The conflict monitor accordingto claim 10 wherein each of said gates comprises a current typeoperational amplifier.
 12. The conflict monitor according to claim 8wherein said second logic circuit comprises a plurality of logicnetworks, one logic network being provided for each overlap indication,each logic network receiving said output signals of each of said firstdetector circuits and said control signals for the corresponding overlapfunction and operable to produce an output signal whenever a firstdetector circuit output signal is received in the absence of thecorresponding control signal, and an AND gate for each overlapindication, each of said AND gates receiving the output signal of thecorresponding second detector circuit and the corresponding logicnetwork, the output signal of each of said AND gates constituting saiderror signal.
 13. The conflict monitor according to claim 12 whereineach logic network comprises a plurality of first NAND gates, one NANDgate being provided for each normal indication and receiving the outputsignal of the corresponding first detector circuit as an input signal,each logic network including circuit means normally providing a secondinput signal to each of said first NAND gates, said programmablecircuits being such that said control signals remove the second inputsignals from the corresponding NAND gates, each network furtherincluding an additonal NAND gate receiving the output signals of each ofsaid first NAND gates as input signals, the output signal of saidadditional NAND gate being the output signal of said logic network. 14.The conflict monitor according to claim 13 wherein each of said gatescomprises a current type operational amplifier.
 15. A conflict monitorfor a traffic control system of the type having a traffic light fordisplaying normal phase and overlap signals to control traffic movementthrough an intersection, certain of said normal phase movements being inconflict with one another, said system including a controller operatingsaid traffic light; the conflict monitor comprising: a plurality offirst input circuits, one input circuit being provided for each normalphase and producing an output signal whenever said normal phase signalis displayed; a first solid state logic network comprised of a pluralityof AND gates each of which receives said output signals of two of saidinput circuits associated with conflicting phases and producing anoutput signal whenever said two phases are in conflict; a second solidstate logic network having a pair of OR gates receiving, respectively,said output signals of first and second groups of said input circuitswith the groups being arranged so that any one phase of either group isin conflict with any phase of the other group, and an AND gateresponsive to the outputs of said OR gates to produce an output signalin the event a conflict occurs between any phase of one group and anyphase of the other group; means under the control of said signalcontroller for disabling said second logic network in the event anormally conflicting signal indication is to be intentionally displayed;a relay operable to switch the signal operation from a sequencing modeto a flashing mode; a timing circuit responsive to the output of each ofsaid AND gates and operable to actuate said relay; an additional inputcircuit associated with each overlap function and producing an outputsignal whenever said overlap indication is being displayed; aprogrammable circuit associated with each overlap function, eachprogrammable circuit receiving the output signal of the correspondingadditional input circuit and producing, in response thereto, controlsignals indicating compatible normal phases during the correspondingoverlap; and an overlap monitoring circuit for each overlap functionincluding a solid state logic network receiving the output signals ofsaid first input circuits, the output signals of said additional inputcircuit associated with the corresponding overlap function and thecontrol signals of said programmable circuit associated with thecorresponding overlap function, each overlap monitoring circuitincluding an AND gate producing an output signal in the event anonpermissible phase display occurs during said overlap, the outputsignal of each of these AND gates also providing an actuating input tosaid timing circuit.